Typically, semiconductor state and dynamic type random access memories are arranged with a plurality of individually addressable memory cells arranged in a matrix of rows and columns. The rows are defined by so called word lines which connect individual outputs of a row decoder to the access transistors of all the memory cells in a particular row. These words lines typically are made of doped polysilicon deposited over an insulating layer covering the surface of the semiconductor substrate. Because of the use of polysilicon, the word line acts like a transmission line by virtue of the distributed resistance and the parasitic capacitance between the word line and the substrate. These electrical properties cause delay in the propagation of signals from one end of the word line to the other.
The memory cells of the array are also arranged into columns with all the memory cells of a particular column connected through an access transistor to a bit line. Each bit line is coupled to a sense amplifier which determines what data was stored in the particular memory cell accessed. The sense amplifier must not be enabled prior to the time that valid data is present on its bit line or a misread will occur. Valid data will be present on the bit line connected to the first memory cell in a row before valid data will be present on the bit line coupled to the last memory cell in the row because of the propagation delay experienced by the select signal from the row decoder in getting to the gate of the access transistor of the last memory cell in the row. Because of this delay, all the sense amplifiers must be held back until the maximum delay in accessing the last cell in the row has occurred regardless of which cell was accessed. This is necessary to insure that the data on the bit line coupled to the selected cell will be valid regardless of which cell in the row is accessed.
Thus it was that clock chains using dummy word lines came into existence. To insure that proper data access was made even where the last cell in a row was accessed, a time-out circuit using a distributed resistance polysilicon dummy word line was devised. This time out circuit was used to emulate the actual propagation delay experienced in accessing the last memory cell in the row. The sense amplifiers were then signalled that even if the last memory cell in the row was accessed, the data on the selected bit line was still valid.
This intentionally caused delay must be equal to or greater than the actual propagation delays in the word lines, or the potential for misreads arises. However, since the aforementioned parasitic effects and polysilicon doping levels can change due to processing variations, it is necessary to design for an extra delay in the dummy word line as a margin of safety to account for these processing variations. This extra delay slows down access times however and is undesirable for high speed random access memories.
Presently, computer simulations are used to predict the time delays that will be experienced in the actual word line circuitry. After prototype chips are manufactured, the actual delays experienced can be measured, and the actual time delay which the dummy word line must be designed for can be determined. However, at that point, it is necessary to go back to the polysilicon level of the process, which is about halfway through the process, and change the polysilicon mask dimensions of the dummy word line. This is quite inconvenient.
The invention defined in the claims appended hereto provides a structure and method to decrease access time by optimizing the emulation of propagation delays in the actual word lines without the necessity of making changes to the polysilicon level masks. The invention provides the distinct advantage of a faster chip without the difficulty and expense of polysilicon level mask changes.